#include "CpuZ80.h"
#include "CpuZ80Macros.h"
#include <cassert>

byte_t CpuZ80::HandleOpcode_CB(byte_t opcode)
{
	switch (opcode)
	{

#pragma region Rotate

	case 0x00: RegB = RotateLeftCircular(RegB);									break;		// RLC B
	case 0x01: RegC = RotateLeftCircular(RegC);									break;		// RLC C
	case 0x02: RegD = RotateLeftCircular(RegD);									break;		// RLC D
	case 0x03: RegE = RotateLeftCircular(RegE);									break;		// RLC E
	case 0x04: RegH = RotateLeftCircular(RegH);									break;		// RLC H
	case 0x05: RegL = RotateLeftCircular(RegL);									break;		// RLC L
	case 0x06: WriteByte(RotateLeftCircular(ReadByte(RegHL)), RegHL);			break;		// RLC (HL)
	case 0x07: RegA = RotateLeftCircular(RegA);									break;		// RLC A

	case 0x08: RegB = RotateRightCircular(RegB);								break;		// RRC B
	case 0x09: RegC = RotateRightCircular(RegC);								break;		// RRC C
	case 0x0A: RegD = RotateRightCircular(RegD);								break;		// RRC D
	case 0x0B: RegE = RotateRightCircular(RegE);								break;		// RRC E
	case 0x0C: RegH = RotateRightCircular(RegH);								break;		// RRC H
	case 0x0D: RegL = RotateRightCircular(RegL);								break;		// RRC L
	case 0x0E: WriteByte(RotateRightCircular(ReadByte(RegHL)), RegHL);			break;		// RRC (HL)
	case 0x0F: RegA = RotateRightCircular(RegA);								break;		// RRC A
	
	case 0x10: RegB = RotateLeft(RegB);											break;		// RL B
	case 0x11: RegC = RotateLeft(RegC);											break;		// RL C
	case 0x12: RegD = RotateLeft(RegD);											break;		// RL D
	case 0x13: RegE = RotateLeft(RegE);											break;		// RL E
	case 0x14: RegH = RotateLeft(RegH);											break;		// RL H
	case 0x15: RegL = RotateLeft(RegL);											break;		// RL L
	case 0x16: WriteByte(RotateLeft(ReadByte(RegHL)), RegHL);					break;		// RL (HL)
	case 0x17: RegA = RotateLeft(RegA);											break;		// RL A

	case 0x18: RegB = RotateRight(RegB);										break;		// RR B
	case 0x19: RegC = RotateRight(RegC);										break;		// RR C
	case 0x1A: RegD = RotateRight(RegD);										break;		// RR D
	case 0x1B: RegE = RotateRight(RegE);										break;		// RR E
	case 0x1C: RegH = RotateRight(RegH);										break;		// RR H
	case 0x1D: RegL = RotateRight(RegL);										break;		// RR L
	case 0x1E: WriteByte(RotateRight(ReadByte(RegHL)), RegHL);					break;		// RR (HL)
	case 0x1F: RegA = RotateRight(RegA);										break;		// RR A

#pragma endregion

#pragma region Shift

	case 0x20: RegB = ShiftLeftArithmetic(RegB);								break;		// SLA B
	case 0x21: RegC = ShiftLeftArithmetic(RegC);								break;		// SLA C
	case 0x22: RegD = ShiftLeftArithmetic(RegD);								break;		// SLA D
	case 0x23: RegE = ShiftLeftArithmetic(RegE);								break;		// SLA E
	case 0x24: RegH = ShiftLeftArithmetic(RegH);								break;		// SLA H
	case 0x25: RegL = ShiftLeftArithmetic(RegL);								break;		// SLA L
	case 0x26: WriteByte(ShiftLeftArithmetic(ReadByte(RegHL)), RegHL);			break;		// SLA (HL)
	case 0x27: RegA = ShiftLeftArithmetic(RegA);								break;		// SLA A

	case 0x28: RegB = ShiftRightArithmetic(RegB);								break;		// SRA B
	case 0x29: RegC = ShiftRightArithmetic(RegC);								break;		// SRA C
	case 0x2A: RegD = ShiftRightArithmetic(RegD);								break;		// SRA D
	case 0x2B: RegE = ShiftRightArithmetic(RegE);								break;		// SRA E
	case 0x2C: RegH = ShiftRightArithmetic(RegH);								break;		// SRA H
	case 0x2D: RegL = ShiftRightArithmetic(RegL);								break;		// SRA L
	case 0x2E: WriteByte(ShiftRightArithmetic(ReadByte(RegHL)), RegHL);			break;		// SRA (HL)
	case 0x2F: RegA = ShiftRightArithmetic(RegA);								break;		// SRA A

	case 0x38: RegB = ShiftRightLogical(RegB);									break;		// SRL B
	case 0x39: RegC = ShiftRightLogical(RegC);									break;		// SRL C
	case 0x3A: RegD = ShiftRightLogical(RegD);									break;		// SRL D
	case 0x3B: RegE = ShiftRightLogical(RegE);									break;		// SRL E
	case 0x3C: RegH = ShiftRightLogical(RegH);									break;		// SRL H
	case 0x3D: RegL = ShiftRightLogical(RegL);									break;		// SRL L
	case 0x3E: WriteByte(ShiftRightLogical(ReadByte(RegHL)), RegHL);			break;		// SRL (HL)
	case 0x3F: RegA = ShiftRightLogical(RegA);									break;		// SRL A

#pragma endregion

#pragma region Bit Test

	case 0x40: BitTest(Bit_0, RegB);									break;  // BIT 0, B
	case 0x41: BitTest(Bit_0, RegC);									break;  // BIT 0, C
	case 0x42: BitTest(Bit_0, RegD);									break;  // BIT 0, D
	case 0x43: BitTest(Bit_0, RegE);									break;  // BIT 0, E
	case 0x44: BitTest(Bit_0, RegH);									break;  // BIT 0, H
	case 0x45: BitTest(Bit_0, RegL);									break;  // BIT 0, L
	case 0x46: BitTest(Bit_0, ReadByte(RegHL));							break;  // BIT 0, (HL)
	case 0x47: BitTest(Bit_0, RegA);									break;  // BIT 0, A

	case 0x48: BitTest(Bit_1, RegB);									break;  // BIT 1, B
	case 0x49: BitTest(Bit_1, RegC);									break;  // BIT 1, C
	case 0x4A: BitTest(Bit_1, RegD);									break;  // BIT 1, D
	case 0x4B: BitTest(Bit_1, RegE);									break;  // BIT 1, E
	case 0x4C: BitTest(Bit_1, RegH);									break;  // BIT 1, H
	case 0x4D: BitTest(Bit_1, RegL);									break;  // BIT 1, L
	case 0x4E: BitTest(Bit_1, ReadByte(RegHL));							break;  // BIT 1, (HL)
	case 0x4F: BitTest(Bit_1, RegA);									break;  // BIT 1, A

	case 0x50: BitTest(Bit_2, RegB);									break;  // BIT 2, B
	case 0x51: BitTest(Bit_2, RegC);									break;  // BIT 2, C
	case 0x52: BitTest(Bit_2, RegD);									break;  // BIT 2, D
	case 0x53: BitTest(Bit_2, RegE);									break;  // BIT 2, E
	case 0x54: BitTest(Bit_2, RegH);									break;  // BIT 2, H
	case 0x55: BitTest(Bit_2, RegL);									break;  // BIT 2, L
	case 0x56: BitTest(Bit_2, ReadByte(RegHL));							break;  // BIT 2, (HL)
	case 0x57: BitTest(Bit_2, RegA);									break;  // BIT 2, A
		   
	case 0x58: BitTest(Bit_3, RegB);									break;  // BIT 3, B
	case 0x59: BitTest(Bit_3, RegC);									break;  // BIT 3, C
	case 0x5A: BitTest(Bit_3, RegD);									break;  // BIT 3, D
	case 0x5B: BitTest(Bit_3, RegE);									break;  // BIT 3, E
	case 0x5C: BitTest(Bit_3, RegH);									break;  // BIT 3, H
	case 0x5D: BitTest(Bit_3, RegL);									break;  // BIT 3, L
	case 0x5E: BitTest(Bit_3, ReadByte(RegHL));							break;  // BIT 3, (HL)
	case 0x5F: BitTest(Bit_3, RegA);									break;  // BIT 3, A

	case 0x60: BitTest(Bit_4, RegB);									break;  // BIT 4, B
	case 0x61: BitTest(Bit_4, RegC);									break;  // BIT 4, C
	case 0x62: BitTest(Bit_4, RegD);									break;  // BIT 4, D
	case 0x63: BitTest(Bit_4, RegE);									break;  // BIT 4, E
	case 0x64: BitTest(Bit_4, RegH);									break;  // BIT 4, H
	case 0x65: BitTest(Bit_4, RegL);									break;  // BIT 4, L
	case 0x66: BitTest(Bit_4, ReadByte(RegHL));							break;  // BIT 4, (HL)
	case 0x67: BitTest(Bit_4, RegA);									break;  // BIT 4, A

	case 0x68: BitTest(Bit_5, RegB);									break;  // BIT 5, B
	case 0x69: BitTest(Bit_5, RegC);									break;  // BIT 5, C
	case 0x6A: BitTest(Bit_5, RegD);									break;  // BIT 5, D
	case 0x6B: BitTest(Bit_5, RegE);									break;  // BIT 5, E
	case 0x6C: BitTest(Bit_5, RegH);									break;  // BIT 5, H
	case 0x6D: BitTest(Bit_5, RegL);									break;  // BIT 5, L
	case 0x6E: BitTest(Bit_5, ReadByte(RegHL));							break;  // BIT 5, (HL)
	case 0x6F: BitTest(Bit_5, RegA);									break;  // BIT 5, A

	case 0x70: BitTest(Bit_6, RegB);									break;  // BIT 6, B
	case 0x71: BitTest(Bit_6, RegC);									break;  // BIT 6, C
	case 0x72: BitTest(Bit_6, RegD);									break;  // BIT 6, D
	case 0x73: BitTest(Bit_6, RegE);									break;  // BIT 6, E
	case 0x74: BitTest(Bit_6, RegH);									break;  // BIT 6, H
	case 0x75: BitTest(Bit_6, RegL);									break;  // BIT 6, L
	case 0x76: BitTest(Bit_6, ReadByte(RegHL));							break;  // BIT 6, (HL)
	case 0x77: BitTest(Bit_6, RegA);									break;  // BIT 6, A

	case 0x78: BitTest(Bit_7, RegB);									break;  // BIT 7, B
	case 0x79: BitTest(Bit_7, RegC);									break;  // BIT 7, C
	case 0x7A: BitTest(Bit_7, RegD);									break;  // BIT 7, D
	case 0x7B: BitTest(Bit_7, RegE);									break;  // BIT 7, E
	case 0x7C: BitTest(Bit_7, RegH);									break;  // BIT 7, H
	case 0x7D: BitTest(Bit_7, RegL);									break;  // BIT 7, L
	case 0x7E: BitTest(Bit_7, ReadByte(RegHL));							break;  // BIT 7, (HL)
	case 0x7F: BitTest(Bit_7, RegA);									break;  // BIT 7, A

#pragma endregion
		
#pragma region Bit Reset

	case 0x80: RegB = BitReset(Bit_0, RegB);							break;  // RES 0, B
	case 0x81: RegC = BitReset(Bit_0, RegC);							break;  // RES 0, C
	case 0x82: RegD = BitReset(Bit_0, RegD);							break;  // RES 0, D
	case 0x83: RegE = BitReset(Bit_0, RegE);							break;  // RES 0, E
	case 0x84: RegH = BitReset(Bit_0, RegH);							break;  // RES 0, H
	case 0x85: RegL = BitReset(Bit_0, RegL);							break;  // RES 0, L
	case 0x86: WriteByte(BitReset(Bit_0, ReadByte(RegHL)), RegHL);		break;  // RES 0, (HL)
	case 0x87: RegA = BitReset(Bit_0, RegA);							break;  // RES 0, A
				  
	case 0x88: RegB = BitReset(Bit_1, RegB);							break;  // RES 1, B
	case 0x89: RegC = BitReset(Bit_1, RegC);							break;  // RES 1, C
	case 0x8A: RegD = BitReset(Bit_1, RegD);							break;  // RES 1, D
	case 0x8B: RegE = BitReset(Bit_1, RegE);							break;  // RES 1, E
	case 0x8C: RegH = BitReset(Bit_1, RegH);							break;  // RES 1, H
	case 0x8D: RegL = BitReset(Bit_1, RegL);							break;  // RES 1, L
	case 0x8E: WriteByte(BitReset(Bit_1, ReadByte(RegHL)), RegHL);		break;  // RES 1, (HL)
	case 0x8F: RegA = BitReset(Bit_1, RegA);							break;  // RES 1, A
				  
	case 0x90: RegB = BitReset(Bit_2, RegB);							break;  // RES 2, B
	case 0x91: RegC = BitReset(Bit_2, RegC);							break;  // RES 2, C
	case 0x92: RegD = BitReset(Bit_2, RegD);							break;  // RES 2, D
	case 0x93: RegE = BitReset(Bit_2, RegE);							break;  // RES 2, E
	case 0x94: RegH = BitReset(Bit_2, RegH);							break;  // RES 2, H
	case 0x95: RegL = BitReset(Bit_2, RegL);							break;  // RES 2, L
	case 0x96: WriteByte(BitReset(Bit_2, ReadByte(RegHL)), RegHL);		break;  // RES 2, (HL)
	case 0x97: RegA = BitReset(Bit_2, RegA);							break;  // RES 2, A
		   		  
	case 0x98: RegB = BitReset(Bit_3, RegB);							break;  // RES 3, B
	case 0x99: RegC = BitReset(Bit_3, RegC);							break;  // RES 3, C
	case 0x9A: RegD = BitReset(Bit_3, RegD);							break;  // RES 3, D
	case 0x9B: RegE = BitReset(Bit_3, RegE);							break;  // RES 3, E
	case 0x9C: RegH = BitReset(Bit_3, RegH);							break;  // RES 3, H
	case 0x9D: RegL = BitReset(Bit_3, RegL);							break;  // RES 3, L
	case 0x9E: WriteByte(BitReset(Bit_3, ReadByte(RegHL)), RegHL);		break;  // RES 3, (HL)
	case 0x9F: RegA = BitReset(Bit_3, RegA);							break;  // RES 3, A
				  
	case 0xA0: RegB = BitReset(Bit_4, RegB);							break;  // RES 4, B
	case 0xA1: RegC = BitReset(Bit_4, RegC);							break;  // RES 4, C
	case 0xA2: RegD = BitReset(Bit_4, RegD);							break;  // RES 4, D
	case 0xA3: RegE = BitReset(Bit_4, RegE);							break;  // RES 4, E
	case 0xA4: RegH = BitReset(Bit_4, RegH);							break;  // RES 4, H
	case 0xA5: RegL = BitReset(Bit_4, RegL);							break;  // RES 4, L
	case 0xA6: WriteByte(BitReset(Bit_4, ReadByte(RegHL)), RegHL);		break;  // RES 4, (HL)
	case 0xA7: RegA = BitReset(Bit_4, RegA);							break;  // RES 4, A
				  
	case 0xA8: RegB = BitReset(Bit_5, RegB);							break;  // RES 5, B
	case 0xA9: RegC = BitReset(Bit_5, RegC);							break;  // RES 5, C
	case 0xAA: RegD = BitReset(Bit_5, RegD);							break;  // RES 5, D
	case 0xAB: RegE = BitReset(Bit_5, RegE);							break;  // RES 5, E
	case 0xAC: RegH = BitReset(Bit_5, RegH);							break;  // RES 5, H
	case 0xAD: RegL = BitReset(Bit_5, RegL);							break;  // RES 5, L
	case 0xAE: WriteByte(BitReset(Bit_5, ReadByte(RegHL)), RegHL);		break;  // RES 5, (HL)
	case 0xAF: RegA = BitReset(Bit_5, RegA);							break;  // RES 5, A
				  
	case 0xB0: RegB = BitReset(Bit_6, RegB);							break;  // RES 6, B
	case 0xB1: RegC = BitReset(Bit_6, RegC);							break;  // RES 6, C
	case 0xB2: RegD = BitReset(Bit_6, RegD);							break;  // RES 6, D
	case 0xB3: RegE = BitReset(Bit_6, RegE);							break;  // RES 6, E
	case 0xB4: RegH = BitReset(Bit_6, RegH);							break;  // RES 6, H
	case 0xB5: RegL = BitReset(Bit_6, RegL);							break;  // RES 6, L
	case 0xB6: WriteByte(BitReset(Bit_6, ReadByte(RegHL)), RegHL);		break;  // RES 6, (HL)
	case 0xB7: RegA = BitReset(Bit_6, RegA);							break;  // RES 6, A
				  
	case 0xB8: RegB = BitReset(Bit_7, RegB);							break;  // RES 7, B
	case 0xB9: RegC = BitReset(Bit_7, RegC);							break;  // RES 7, C
	case 0xBA: RegD = BitReset(Bit_7, RegD);							break;  // RES 7, D
	case 0xBB: RegE = BitReset(Bit_7, RegE);							break;  // RES 7, E
	case 0xBC: RegH = BitReset(Bit_7, RegH);							break;  // RES 7, H
	case 0xBD: RegL = BitReset(Bit_7, RegL);							break;  // RES 7, L
	case 0xBE: WriteByte(BitReset(Bit_7, ReadByte(RegHL)), RegHL);		break;  // RES 7, (HL)
	case 0xBF: RegA = BitReset(Bit_7, RegA);							break;  // RES 7, A

#pragma endregion

#pragma region Bit Set

	case 0xC0: RegB = BitSet(Bit_0, RegB);									break;  // SET 0, B
	case 0xC1: RegC = BitSet(Bit_0, RegC);									break;  // SET 0, C
	case 0xC2: RegD = BitSet(Bit_0, RegD);									break;  // SET 0, D
	case 0xC3: RegE = BitSet(Bit_0, RegE);									break;  // SET 0, E
	case 0xC4: RegH = BitSet(Bit_0, RegH);									break;  // SET 0, H
	case 0xC5: RegL = BitSet(Bit_0, RegL);									break;  // SET 0, L
	case 0xC6: WriteByte(BitSet(Bit_0, ReadByte(RegHL)), RegHL);			break;  // SET 0, (HL)
	case 0xC7: RegA = BitSet(Bit_0, RegA);									break;  // SET 0, A
				  															   
	case 0xC8: RegB = BitSet(Bit_1, RegB);									break;  // SET 1, B
	case 0xC9: RegC = BitSet(Bit_1, RegC);									break;  // SET 1, C
	case 0xCA: RegD = BitSet(Bit_1, RegD);									break;  // SET 1, D
	case 0xCB: RegE = BitSet(Bit_1, RegE);									break;  // SET 1, E
	case 0xCC: RegH = BitSet(Bit_1, RegH);									break;  // SET 1, H
	case 0xCD: RegL = BitSet(Bit_1, RegL);									break;  // SET 1, L
	case 0xCE: WriteByte(BitSet(Bit_1, ReadByte(RegHL)), RegHL);			break;  // SET 1, (HL)
	case 0xCF: RegA = BitSet(Bit_1, RegA);									break;  // SET 1, A
				  															   
	case 0xD0: RegB = BitSet(Bit_2, RegB);									break;  // SET 2, B
	case 0xD1: RegC = BitSet(Bit_2, RegC);									break;  // SET 2, C
	case 0xD2: RegD = BitSet(Bit_2, RegD);									break;  // SET 2, D
	case 0xD3: RegE = BitSet(Bit_2, RegE);									break;  // SET 2, E
	case 0xD4: RegH = BitSet(Bit_2, RegH);									break;  // SET 2, H
	case 0xD5: RegL = BitSet(Bit_2, RegL);									break;  // SET 2, L
	case 0xD6: WriteByte(BitSet(Bit_2, ReadByte(RegHL)), RegHL);			break;  // SET 2, (HL)
	case 0xD7: RegA = BitSet(Bit_2, RegA);									break;  // SET 2, A
		   		  															   
	case 0xD8: RegB = BitSet(Bit_3, RegB);									break;  // SET 3, B
	case 0xD9: RegC = BitSet(Bit_3, RegC);									break;  // SET 3, C
	case 0xDA: RegD = BitSet(Bit_3, RegD);									break;  // SET 3, D
	case 0xDB: RegE = BitSet(Bit_3, RegE);									break;  // SET 3, E
	case 0xDC: RegH = BitSet(Bit_3, RegH);									break;  // SET 3, H
	case 0xDD: RegL = BitSet(Bit_3, RegL);									break;  // SET 3, L
	case 0xDE: WriteByte(BitSet(Bit_3, ReadByte(RegHL)), RegHL);			break;  // SET 3, (HL)
	case 0xDF: RegA = BitSet(Bit_3, RegA);									break;  // SET 3, A
				  															   
	case 0xE0: RegB = BitSet(Bit_4, RegB);									break;  // SET 4, B
	case 0xE1: RegC = BitSet(Bit_4, RegC);									break;  // SET 4, C
	case 0xE2: RegD = BitSet(Bit_4, RegD);									break;  // SET 4, D
	case 0xE3: RegE = BitSet(Bit_4, RegE);									break;  // SET 4, E
	case 0xE4: RegH = BitSet(Bit_4, RegH);									break;  // SET 4, H
	case 0xE5: RegL = BitSet(Bit_4, RegL);									break;  // SET 4, L
	case 0xE6: WriteByte(BitSet(Bit_4, ReadByte(RegHL)), RegHL);			break;  // SET 4, (HL)
	case 0xE7: RegA = BitSet(Bit_4, RegA);									break;  // SET 4, A
				  															   
	case 0xE8: RegB = BitSet(Bit_5, RegB);									break;  // SET 5, B
	case 0xE9: RegC = BitSet(Bit_5, RegC);									break;  // SET 5, C
	case 0xEA: RegD = BitSet(Bit_5, RegD);									break;  // SET 5, D
	case 0xEB: RegE = BitSet(Bit_5, RegE);									break;  // SET 5, E
	case 0xEC: RegH = BitSet(Bit_5, RegH);									break;  // SET 5, H
	case 0xED: RegL = BitSet(Bit_5, RegL);									break;  // SET 5, L
	case 0xEE: WriteByte(BitSet(Bit_5, ReadByte(RegHL)), RegHL);			break;  // SET 5, (HL)
	case 0xEF: RegA = BitSet(Bit_5, RegA);									break;  // SET 5, A
				  															   
	case 0xF0: RegB = BitSet(Bit_6, RegB);									break;  // SET 6, B
	case 0xF1: RegC = BitSet(Bit_6, RegC);									break;  // SET 6, C
	case 0xF2: RegD = BitSet(Bit_6, RegD);									break;  // SET 6, D
	case 0xF3: RegE = BitSet(Bit_6, RegE);									break;  // SET 6, E
	case 0xF4: RegH = BitSet(Bit_6, RegH);									break;  // SET 6, H
	case 0xF5: RegL = BitSet(Bit_6, RegL);									break;  // SET 6, L
	case 0xF6: WriteByte(BitSet(Bit_6, ReadByte(RegHL)), RegHL);			break;  // SET 6, (HL)
	case 0xF7: RegA = BitSet(Bit_6, RegA);									break;  // SET 6, A
				  															   
	case 0xF8: RegB = BitSet(Bit_7, RegB);									break;  // SET 7, B
	case 0xF9: RegC = BitSet(Bit_7, RegC);									break;  // SET 7, C
	case 0xFA: RegD = BitSet(Bit_7, RegD);									break;  // SET 7, D
	case 0xFB: RegE = BitSet(Bit_7, RegE);									break;  // SET 7, E
	case 0xFC: RegH = BitSet(Bit_7, RegH);									break;  // SET 7, H
	case 0xFD: RegL = BitSet(Bit_7, RegL);									break;  // SET 7, L
	case 0xFE: WriteByte(BitSet(Bit_7, ReadByte(RegHL)), RegHL);			break;  // SET 7, (HL)
	case 0xFF: RegA = BitSet(Bit_7, RegA);									break;  // SET 7, A

#pragma endregion

#pragma region Undocumented 

	case 0x30: RegB = BitSet(Bit_0, ShiftLeftLogical(RegB));						break; // SLS B
	case 0x31: RegC = BitSet(Bit_0, ShiftLeftLogical(RegC));						break; // SLS C 
	case 0x32: RegD = BitSet(Bit_0, ShiftLeftLogical(RegD));						break; // SLS D 
	case 0x33: RegE = BitSet(Bit_0, ShiftLeftLogical(RegE));						break; // SLS E 
	case 0x34: RegH = BitSet(Bit_0, ShiftLeftLogical(RegH));						break; // SLS H 
	case 0x35: RegL = BitSet(Bit_0, ShiftLeftLogical(RegL));						break; // SLS L 
	case 0x36: WriteByte(BitSet(Bit_0, ShiftLeftLogical(ReadByte(RegHL))), RegHL);  break; // SLS (HL)
	case 0x37: RegA = BitSet(Bit_0, ShiftLeftLogical(RegA));						break; // SLS A

#pragma endregion

	default:
		assert(false && "Unrecognized Opcode");
		break;
	}

	return m_cyclesCB[opcode];
}

